Semiconductors are the foundation of the technology sector and one of the most analytically demanding industries in the public markets. The reason is a structural collision: supply is slow, lumpy, and brutally capital-intensive (a leading-edge fab takes years and tens of billions of dollars and must run near full to cover its fixed costs), while end demand is fast and volatile (it swings with phones, PCs, datacenters, autos, and industrial spending). That mismatch — physically grounded capacity versus quicksilver demand, amplified by inventory behavior up the supply chain — makes the sector deeply cyclical, concentrates extraordinary power in a handful of chokepoint companies, and means the dominant question for any chip stock is rarely "is the company good?" but "where are we in the cycle, and what is this company's structural position within it?" This section is the industry playbook that frames those two questions; its three child nodes drill into the mechanics.

What the section covers (and what it doesn't)

This is a fundamentals/context playbook, not a technical-analysis branch. It defines how the semiconductor industry works as a business and a cycle so that any downstream price or setup analysis on a chip ticker is read against the right backdrop. It deliberately does not cover: specific company analysis (that's per-ticker), general macro/regime mechanics (the broader macro nodes), or chart patterns and entries (the Technical Analysis and Swing Trading branches). It sits alongside sibling industry playbooks under Sector & Industry Playbooks > Technology.

A few scale facts to anchor the section. Semiconductors are a ~$600–800B+ annual industry that the WSTS projected to grow ~22% to about $772B in 2025 and toward ~$975B in 2026, led by Logic and Memory on AI/datacenter demand (WSTS, via Semiconductor Digest). By product, 2024 sales were roughly Logic ~$213B and Memory ~$165B (the latter after a ~79% rebound) per SIA, with Analog the next-largest category at roughly $100B+ (estimates range ~$88B–$103B depending on the firm and definition; ~16–17% of the total market) (SIA 2024 results; analog range from GMInsights ~$87.5B and Precedence Research ~$101B) — a useful reminder that the segments behave very differently and should never be treated as one homogeneous "chips" bucket. Sector beta is high: the PHLX Semiconductor Index (SOX) — the 30 largest U.S.-traded chip names — routinely swings far more than the S&P 500, and as the child nodes document, chip stocks are widely observed to lead the fundamentals (a commonly cited rule of thumb of roughly 6–12 months), so the tape tends to move before the news.

The core tension

Everything in this playbook traces back to one trade-off: capital intensity vs. control vs. flexibility. Owning a fab gives a company control over its most strategic asset but saddles it with enormous fixed costs, multi-year capex commitments, and a depreciation drag that punishes margins after every build-out. Not owning one (the fabless model) yields high margins and flexibility but surrenders control to a near-monopoly foundry — concentrating the entire leading-edge ecosystem into a single geographic chokepoint. The same forces that lowered barriers for chip designers created extreme concentration in chip manufacturing and chip equipment. The cycle, the business models, and the capex machinery are three views of this one tension.

When it matters vs. when it doesn't

This playbook is decisive when analyzing any name whose fortunes ride the chip cycle — foundries, memory makers, equipment vendors, and broad-line logic. It matters most near suspected cycle turns, around earnings (where guidance, not just results, moves these stocks violently), and for the equipment vendors whose revenue is customers' capex. It matters less for the least-cyclical corners (analog/embedded names with sticky, decade-long design sockets) and is largely irrelevant to non-semiconductor tech. The single biggest cross-cutting trap the whole section guards against: trailing-valuation anchoring — a cyclical chip stock looks "cheapest" (low trailing P/E) exactly when earnings are about to collapse at the peak, and "most expensive" (losses, high P/E) at the trough.

Map of the sub-topics

Three child nodes decompose the sector; read them for the depth this overview only points to:

• Cyclicality & Inventory (001-cyclicality-and-inventory) — the boom-bust engine. Covers the overlapping capacity cycle (fabs committed 18–36 months ahead) and inventory cycle (the bullwhip effect), the leading-indicator dashboard (book-to-bill, days-of-inventory, lead times, ASPs, utilization), why the stock leads the fundamentals, and how cyclicality varies sharply by segment (memory most cyclical, analog least). The most operationally important node for timing bias.

• Fabless vs. Foundry vs. IDM (002-fabless-vs-foundry-vs-idm) — the structural business-model lens. Defines who designs vs. who manufactures, the divergent economics (asset-light fabless companies typically run materially higher gross margins than capital-heavy foundries), TSMC's commanding pure-play foundry lead (commonly cited around the mid-60% range and rising — e.g. ~64% in 2024 per Counterpoint/IDC, with some quarterly prints toward ~70%), and why the categories are now porous (Intel's IDM 2.0, Samsung's hybrid model). This is the first-pass decoder for which financial-statement risks a given chip company carries.

• Capex & Equipment (003-capex-and-equipment) — the wafer-fab-equipment (WFE) supply chain. Covers who spends (TSMC, memory makers), who sells (the per-step near-monopolies: ASML in lithography, Applied Materials and Lam in deposition/etch, KLA in metrology, Tokyo Electron), why equipment bookings lead the whole cycle, and the contrarian truth that record capex at a top warns of the next bust rather than confirming strength.

Read together, the three answer the section's master question in sequence: cyclicality tells you when, business model tells you what risk a company carries, and capex/equipment gives the earliest leading read and the highest-conviction quality businesses.

Standing & evidence

None of this is contested at the level of existence — the cycle, the model split, and the capex chokepoints are decades-documented industry structure, not folklore. The genuine open debates, surfaced honestly in the children, are about magnitude and durability: whether aggregate cyclicality is structurally dampening (segment-level cyclicality clearly is not), whether the AI build-out is a true supercycle or an ordinary memory cycle that will end the same way prior ones did, and whether ASML's EUV monopoly is durable against a Chinese domestic effort. Forecast dollar figures from WSTS, SEMI, Gartner, and TechInsights routinely differ by billions and are revised quarterly — treat any single number as a point estimate in a wide band.

Sources

• WSTS / Semiconductor Digest — global market approaching ~$1T (2025 ~$772B, 2026 ~$975B), Logic/Memory led
• SIA — global semiconductor sales +19.1% to $627.6B in 2024; Logic $212.6B, Memory $165.1B (+78.9%)
• Analog 2024 market (estimates vary): GMInsights ~$87.5B and Precedence Research ~$101B
• Counterpoint / IDC via Focus Taiwan — TSMC pure-play foundry share ~64% (2024), forecast ~66% (2025)
• Child nodes (primary depth + their own cited sources): 001-cyclicality-and-inventory, 002-fabless-vs-foundry-vs-idm, 003-capex-and-equipment

Dispute flagged: industry-size and segment figures vary by source (WSTS vs. Gartner vs. SIA differ by definition and are revised) — the numbers above are directional anchors, not audited precision. The "AI supercycle vs. ordinary cycle" and "is cyclicality structurally dampening?" questions are genuinely unresolved; the children carry the detailed evidence and caveats.