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Capex & Equipment

Updated Jun 24, 2026 at 8:22pm

Research Draft High 1,178 words

Building a chip fab is one of the most capital-intensive activities in the global economy: a leading-edge logic fab can cost upward of $20 billion before it ships a single wafer, and the single most expensive tools inside it — ASML's EUV lithography scanners — run from roughly $183 million for a Low-NA system to about $380 million for a High-NA machine (Tom's Hardware). The core tension for investors is that this spending is enormous, lumpy, and pro-cyclical: chipmakers commit multi-year capex budgets based on demand forecasts that are frequently wrong, so the wafer-fab-equipment (WFE) supply chain swings between feast and famine — while the four-to-five vendors who sell the tools sit on near-monopoly chokepoints that make them, paradoxically, both highly cyclical and structurally advantaged.

The structure: who spends, who sells

The spenders (capex side). Three buyer groups drive WFE demand. (1) Leading-edge foundry/logic — dominated by TSMC, whose 2026 capex is guided to the high end of a roughly $52–56 billion range, a single-company figure that exceeds the entire WFE market of a few years ago (SCMP). (2) Memory — Samsung, SK Hynix, Micron — whose spending is the most violently cyclical, currently rebounding on DRAM tightness and the high-bandwidth-memory (HBM) buildout for AI accelerators (SemiAnalysis). (3) Trailing-edge/mature nodes, where China has been a large but politically constrained buyer.

The sellers (equipment side). Five vendors control nearly the entire advanced-node toolset, each dominant in a different process step (PublicComps primer):

  • Lithography — ASML. Sole maker of EUV scanners; an effective monopoly at the single most critical chokepoint in the supply chain.
  • Deposition — Applied Materials (laying down films); ASM dominates atomic-layer deposition specifically.
  • Etch — Lam Research (carving features); benefits structurally as devices go 3D (3D NAND, gate-all-around).
  • Process control / metrology — KLA, with a reported >50% share of defect inspection.
  • Coaters / track & advanced packaging — Tokyo Electron, plus BESI in packaging.

This near-monopoly-per-step structure is why semicap is a favored quality-compounding sector despite its cyclicality.

How it's used in practice

Capex and equipment data are read at two levels.

As a fundamental driver for the equipment vendors. WFE spending is these companies' revenue. Analysts track the global WFE number (commonly cited in the ~$100–116 billion range for 2025, with estimates varying by source — e.g. SEMI/nextmsc, Gartner forecasts) and decompose it by node and by customer. Two vendor-quality signals matter: the service/aftermarket mix (installed-base revenue that recurs regardless of new-tool orders — Lam and others highlight this as a margin and stability buffer), and node leverage (etch/deposition intensity rises as structures go vertical, expanding the addressable market per wafer).

As a leading indicator for the whole chip cycle. Because tools are ordered before fabs ramp and chips ship, equipment metrics lead the broader semiconductor cycle:

  • SEMI billings / book-to-bill — monthly North American + global equipment billings; a book-to-bill above 1.0 signals expansion.
  • ASML's order book and bookings — watched as the cleanest read on leading-edge intent, since EUV is non-substitutable.
  • Capex intensity — capex as a % of revenue (for chipmakers) and semicap revenue as a % of total semiconductor revenue (~15–16% currently, up from a historical 10–13% per the PublicComps primer). Rising intensity warns of future oversupply.

Adoption, debate & evidence

The use of WFE/capex as a cycle barometer is mainstream among semiconductor analysts and is not seriously contested — the order-to-revenue lead is mechanical. The genuine debates are about magnitude and timing:

  • AI-driven supercycle vs. ordinary cycle. Bulls argue AI compute structurally lifts equipment spending to records: SEMI projects total semiconductor equipment sales (WFE + test + assembly/packaging) to reach a record ~$156B in 2027, of which WFE specifically is forecast at ~$135B — don't conflate the two (SEMI press release; EE Times). Skeptics note every prior memory boom ended the same way — historically a 4–7 quarter boom followed by a 4–8 quarter bust with revenue declines of ~25–40% (UncoverAlpha). The cleanest historical analog: DRAM prices peaked in late 1995 then fell ~51% in 1996 and another ~65% in 1997.
  • The depreciation trap. Heavy capex becomes a multi-year depreciation drag on margins after the fact. TSMC has deliberately leaned on existing EUV tools plus multi-patterning to defer the most expensive High-NA purchases and avoid that drag (01.co analysis) — a reminder that record capex budgets don't always translate to record tool orders.
  • The China/geopolitics wildcard. WFE forecasts shift on export controls; China's share of WFE was projected to fall to ~31% in 2025 from ~36% in 2024 (nextmsc). A domestic Chinese EUV effort, if real, would eventually threaten ASML's monopoly thesis.

Forecast numbers from Gartner, SEMI, and TechInsights routinely differ by several billion dollars and get revised quarterly — treat any single WFE figure as a point estimate within a wide band, not a fact.

Strengths & limitations

When the lens works: It is genuinely leading. Equipment bookings and book-to-bill turn before fab output and before chip-company revenue, giving an early read on the cycle. The per-step monopolies make the vendors high-quality, high-margin businesses with pricing power and recurring service revenue — they often outperform the chipmakers they supply across a full cycle.

When it fails / #1 misuse: The biggest error is treating capex announcements as bullish in themselves. Record capex at a cycle top is a contrarian warning — it signals the oversupply that produces the next bust, and the depreciation that crushes margins afterward. A second misuse is conflating capex budget with equipment orders: budgets can be deferred, re-allocated to mature nodes, or spent on construction rather than tools. Third, the data is lumpy and revised — a single soft quarter of billings can be timing noise (customers hedging order placement against ASML's long lead times), not a trend break.

Sources

Disputes flagged: WFE dollar figures differ materially across Gartner/SEMI/TechInsights and are revised quarterly — all are point estimates. The "AI supercycle vs. ordinary memory cycle" question is genuinely unresolved. ASML's EUV monopoly durability is contested pending any viable Chinese domestic EUV tool.